Typical integrated circuit manufacturing processes often involve the creation of openings in various materials by selective etching. For example, openings, termed "trenches" are often made in a substrate such as silicon to provide isolation between individual devices or to provide capacitive charge storage. Other openings, termed "vias" or "windows" or "contact holes" are often made in dielectric layers to facilitate connection between two layers of metallization or between a metallization layer and an active region of a transistor. Usually these openings are created by depositing a photoresist upon the material in which the opening is to be made. Portions of the photoresist are exposed to light. Either the exposed or the unexposed portion of the photoresist is washed away (depending upon whether a positive or negative photoresist is employed) leaving selected portions of the underlying material exposed. With the remaining resist serving as a mask, the exposed portions of the underlying material are etched through to create openings. The openings may be subsequently filled with appropriate materials. For example, if the opening is a trench, the trench may be filled with insulative material to facilitate inter-device isolation. If the trench is to be used for capacitive storage, it may be lined with one or more layers of conductive material. Vias or windows may be subsequently filled with a conductive material, for example a metal, thus providing a conductive link between two layers of metallization or between a source/drain and an overlying metallization.
In general terms, it is usually considered desirable to faithfully reproduce the patterned resist in the underlying material. Attempts to make the underlying feature size (or opening) either larger or smaller than the overlying patterned resist features have generally suffered from wafer-to-wafer or within-wafer or within-chip non-uniformities.
Processes which faithfully reproduce the patterned resist in the underlying material (with vertical walls) may be termed "zero delta" processes because there is no difference in feature width between the resist and the underlying material. Occasionally, zero delta processes are subsequently modified to create features with sloping walls. Examples of zero delta processes modified to create sloping walls are the formation of sloped vias (for improved metal step coverage) and the formation of metal runners with sloped walls (for improved dielectric coverage). However, the smallest between-feature width as well as the smallest opening in zero delta processes (even with sloped walls) is generally limited by lithography.
Those concerned with the development of semiconductor devices and processes have continually sought methods for producing openings including vias and windows and trenches with dimensions below the limits achievable by straightforward lithography.